The present invention relates to a fabrication technology of a semiconductor device, and more particularly, to a semiconductor device with a bulb type recess gate and a method for fabricating the same.
As semiconductor devices are highly integrated, a portion of an active region is etched to form a recess in a semiconductor substrate and a gate is formed on the recess. The process of forming the recess gate is important for the fabrication of the semiconductor devices. Compared with a typical planar gate structure, the recess gate has a longer gate length and a wider channel area. Therefore, the formation of the recess gate can improve electrical characteristics of the semiconductor device, such as a threshold voltage and a refresh time.
However, as semiconductor devices are scaled down, patterns become finer and a gap between components is reduced. Hence, there is a need for a technology that can further increase a channel area. As one example, a process of forming a bulb type recess gate is proposed which can increase a channel area by increasing an area of a lower portion of a recess. More specifically, the bulb type recess includes a neck pattern and a bulb pattern. The neck pattern is formed by etching a semiconductor substrate using a hard mask pattern as an etching mask. The hard mask pattern opens a region where a recess is formed. The bulb pattern is formed by forming spacer insulating layers on sidewalls of the neck pattern and isotropically etching the semiconductor substrate under the neck pattern.
FIG. 1 is a sectional view of a profile of a typical recess and a bulb type recess. Referring to FIG. 1, a lower portion of a bulb type recess shown on the right side of FIG. 1 is a bulb pattern having a spherical shape. Therefore, compared with a typical recess shown on the left side of FIG. 1, the bulb type recess can secure a wider channel area. As the bulb pattern is larger, the channel area can be further widened.
However, a void is formed when a polysilicon electrode for a gate pattern is deposited on the bulb type recess. This result is because the neck pattern disposed at an upper portion of the recess is narrower than the bulb pattern disposed at a lower portion of the recess. Thus, the neck pattern is first filled with the polysilicon before the bulb pattern is completely filled. In case where the size of the void is small, the void does not greatly affect the characteristics of the device (see FIG. 2A). However, as the bulb pattern is larger compared with the neck pattern in the bulb type recess, the size of the void increases (see FIG. 2B) The increase in the size of the void may badly affect the electrical characteristics of the device.
On the other hand, when a large neck pattern is formed considering the size of the bulb pattern, the size of the void can be reduced. However, an overlay margin with respect to the gate pattern formed on the recess is reduced. Thus, a misalignment may occur so that an upper portion of the bulb type recess is exposed out of the gate pattern (see FIG. 3). This misalignment may have a bad effect on the electrical characteristics of the device.
Therefore, there is a need for a technique that can reduce the size of the void, while maintaining the size of the bulb pattern and the overlay margin with respect to the gate pattern formed on the recess.